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GL811S usb 2.0 to ata/atapi bridge controller datasheet revision 1.02 apr. 13, 2007 genesys logic, inc.
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 2 copyright: copyright ? 2007 genesys logic incorporated. all rights reserv ed. no part of the materials may be reproduced in any form or by any means without prio r written consent of genesys logic, inc. disclaimer: all materials are provided "as is" without express or implied warranty of any kind. no license or right is granted under any pat ent or trademark of genesys logic inc.. genesys logic hereby disclaims all warranties and conditions in regard to materials, including all wa rranties, implied or express, of merchantability, fitness for any partic ular purpose, and non-infringement of intellectual property. in no e vent shall genesys logic be liable for any damages including, without limita tion, damages resulting from loss of information or profits. please be adv ised that the materials may contain errors or ommisions. genesys logic may make changes to the materials or to the products described therein at a ny time without notice. trademarks: is a registered trademark of genesys logic, inc. all trademarks are the properties of their respect ive owners. office: genesys logic, inc. 12f, no. 205, sec. 3, beishin rd., shindian city, taipei, taiwan tel: (886-2) 8913-1888 fax: (886-2) 6629-6168 http://www.genesyslogic.com
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 3 revision history revision date description 1.00 03/09/2006 first release 1.01 05/25/2006 modify GL811S 48 pin tqfp package, figure 7.2, p.37 1.02 04/13/2007 remove 48pin tqfp pinout, p.9 and 48pin tqfp dimens ion, p.35
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 4 table of contents chapter 1 general description..................... .............................. 7 chapter 2 features ................................ .............................................. 8 chapter 3 pin assignment .......................... ...................................... 9 3.1 p inouts ................................................... ................................................... 9 3.2 p in l ist ................................................... ................................................. 11 3.3 p in d escriptions ................................................... ................................ 12 chapter 4 block diagram........................... ................................... 16 chapter 5 function description .................... ........................... 17 5.1 utm................................................ ................................................... ...... 17 5.2 sie................................................ ................................................... ......... 17 5.3 ep0/ep3 fifo ............................................... ......................................... 17 5.4 b ulk fifo ............................................... ............................................... 17 5.5 ide i nterface ................................................... .................................... 17 5.6 o peration r egister ................................................... .......................... 17 5.7 spi i nterface ................................................... ..................................... 17 chapter 6 electrical characteristics.............. ................. 18 6.1 a bsolute m aximum r atings ................................................... ........... 18 6.2 t emperature c onditions ................................................... ................ 18 6.3 dc c haracteristics ................................................... ......................... 18 6.3.1 i/o type digital pins ........................ ............................................... 18 6.3.2 d+/ d- ....................................... ................................................... ..... 19 6.3.3 switching characteristics.................... ........................................... 19 6.4 ac c haracteristics - ata/ atapi .............................................. ..... 19 6.4.1 register transfers / pio data transfers ...... ............................... 21 6.4.2 multiword dma data transfer .................. .................................... 23 6.4.3 ultra dma data transfer...................... .......................................... 27 6.5 ac c haracteristics - usb 2.0................................................ ............ 34 chapter 7 package dimension....................... .............................. 35 chapter 8 ordering information .................... ........................ 37
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 5 list of figures f igure 3.1 - 48 p in lqfp p inout d iagram ................................................... ................. 9 f igure 3.2 - 64 p in lqfp p inout d iagram ................................................... ............... 10 f igure 4.1 - b lock d iagram ................................................... ...................................... 16 f igure 6.1 - i nitiating a m ultiword dma d ata b urst .......................................... 24 f igure 6.2 - s ustaining a m ultiword dma d ata b urst ........................................ 25 f igure 6.3 - d evice t erminating a m ultiword dma d ata b urst ....................... 25 f igure 6.4 - h ost terminating a m ultiword dma d ata b urst ........................... 26 f igure 6.5 - i nitiating an u ltra dma d ata -i n b urst ............................................ 28 f igure 6.6 - s ustained u ltra dma d ata -i n b urst .................................................. 2 8 f igure 6.7 - h ost p ausing an u ltra dma d ata -i n b urst ...................................... 29 f igure 6.8 - d evice t erminating an u ltra dma d ata -i n b urst ......................... 29 f igure 6.9 - h ost t erminating an u ltra dma d ata -i n b urst ............................. 30 f igure 6.10 - i nitiating an u ltra dma d ata -o ut b urst ...................................... 31 f igure 6.11 - s ustained u ltra dma d ata -o ut b urst ............................................ 31 f igure 6.12 - d evice p ausing an u ltra dma d ata -o ut b urst ............................. 32 f igure 6.13 - h ost terminating an u ltra dma data - out burst ......................... 33 f igure 6.14 - d evice t erminating an u ltra dma d ata -o ut b urst .................... 34 f igure 7.1 ? GL811S 48 p in lqfp p ackage ................................................... ............. 35 f igure 7.2 ? GL811S 64 p in lqfp p ackage ................................................... ............. 36
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 6 list of tables t able 3.1 - 48 p in l ist ................................................... .................................................. 1 1 t able 3.2 - 64 p in l ist ................................................... .................................................. 1 1 t able 3.3 ? 48 p in d escriptions ................................................... ................................. 12 t able 3.4 - 64 p in d escriptions ................................................... ................................. 13 t able 6.1 - m aximum r atings ................................................... ................................... 18 t able 6.2 - t emperature c onditions ................................................... ...................... 18 t able 6.3 - i/o t ype digital pins ................................................... ............................... 18 t able 6.4 - d+/ d-................................................. ................................................... ......... 19 t able 6.5 - s witching c haracteristics ................................................... ................. 19 t able 6.5 - u ltra dma data burst timing requirements ..................................... 27 t able 8.1 - o rdering i nformation ................................................... .......................... 37
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 7 chapter 1 general description the GL811S is a highly-compatible, low cost usb 2.0 to ata / atapi bridge controller, which integrates genesys logic own design high speed utmi (usb 2.0 t ransceiver macrocell interface) transceiver. as a one-chip solution which complies with universa l serial bus specification rev. 2.0 and ata / atapi -6 specification rev 1.0, the GL811S can support vario us kinds of ata / atapi device. there are totally 4 endpoints in the GL811S controller, control (0), bu lk in (1), bulk out (2), and interrupt (3). by comp lies with the usb storage class specification ver.1.0 (bulk o nly protocol), the GL811S can support not only plug and play but also windows xp/ 2000/ me default driver. the GL811S uses 12mhz crystal and slew-rate control led pads to reduce the emi issue. with 48-pin lqfp (7mmx7mm) package, the GL811S is the best cost/ per formance solution to fit different situations in th e usb 2.0 high speed storage class applications such as h ard disk, cd-rom, cd-r / rw and dvd-rom.
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 8 chapter 2 features complies with universal serial bus specification rev. 2.0. complies with ata/atapi-6 specification rev 1.0. complies with usb storage class specification ver .1.0. (bulk only protocol) operating system supported: win xp / 2000 / me / 98 / 98se; mac os 9.x / 10.x. integrated usb 2.0 transceiver macrocell interfac e (utmi) transceiver and serial interface engine (s ie). support 4 endpoints: control (0) / bulk read (1) / bulk write (2) / interrupt (3). 64 / 512 bytes data payload for full / high speed bulk endpoint. support 16-bit multiword dma mode and ultra dma m ode interface (ultra 33 / 66). embedded turbo 8051. rom size: 12k words; ram size: 1280 bytes. (bulk buffer: 512 words, mc ram: 256 bytes) supports power down mode and usb suspend indicato r. supports usb 2.0 test mode features. supports 4 gpios for programmable ap (48 pin pack age). supports 8 gpios for programmable ap (64 pin pack age). supports device power control for power on/off wh en running suspend mode. supports 32 bit and 48 bit lba hard disk. provides led indicator for full speed and high sp eed (only for 64 pin package). using 12 mhz external clock to provide better emi . 3.3v i/os (5v tolerant) 5v tolerance pad for ide interface. operates at 5v voltage (built-in 5v to 3.3v & 3.3 v to 1.8v regulator) supports wakeup ability. available in 48-pin/64-pin lqfp package types. provides spi interface (only for 64 pin package). provides uart interface (only for 64 pin package) .
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 9 chapter 3 pin assignment 3.1 pinouts dd12 1 xi 25 dd3 2 pio0 3 dd11 4 dd4 5 dd10 6 dvdd1 7 dd5 8 dd9 9 dd6 10 dd8 11 dd7 12 test 26 cs1_ 27 d_pwr_ctl 28 5v_in 29 3v3_out 30 cs0_ 31 da2 32 da0 33 da1 34 intrq 35 dmack_ 36 figure 3.1 - 48 pin lqfp pinout diagram
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 10 GL811S lqfp - 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dd12 dd3 pio2 pio0 pio1 dd11 dd4 dd10 dvdd dgnd dd5 dd9 dd6 dd8 dd7 nc 1 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 dmack_ intrq da1 da0 u_tx u_rx da2 cs0_ 3v3_out 5v_in d_pwr_ctl cs1_ test nc dgnd xi xo x_power avdd1 rref agnd1 dp dm avdd3 agnd dgnd reset# usb_pwr hd_rst# nc nc nc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 iordy nc dior_ diow_ dmarq dd15 dgnd dvdd dd0 dd14 dd1 dd13 dd2 gpio1 f_led h_led 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 49 figure 3.2 - 64 pin lqfp pinout diagram
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 11 3.2 pin list table 3.1 - 48 pin list pin# pin name type pin# pin name type pin# pin name type pin# pin name type 1 dd12 b 13 hd_rst# o 25 xi i 37 iordy i 2 dd3 b 14 usb_pwr b 26 test i 38 dior_ o 3 pio0 b 15 reset# i 27 cs1_ o 39 diow_ o 4 dd11 b 16 agnd1 p 28 d_pwr_ctl b 40 dmarq i 5 dd4 b 17 avdd1 p 29 5v_in p 41 dd15 b 6 dd10 b 18 dm b 30 3v3_out p 42 dvdd p 7 dvdd1 p 19 dp b 31 cs0_ o 43 dd0 b 8 dd5 b 20 agnd2 p 32 da2 o 44 dd14 b 9 dd9 b 21 vref a 33 da0 o 45 dd1 b 10 dd6 b 22 avcc2 p 34 da1 o 46 dd13 b 11 dd8 b 23 x-power p 35 intrq i 47 dd2 b 12 dd7 b 24 xo b 36 dmack_ o 48 gpio1 b table 3.2 - 64 pin list pin# pin name type pin# pin name type pin# pin name type pin# pin name type 1 dd12 b 17 nc 33 xi i 49 iordy i 2 dd3 b 18 nc 34 dgnd p 50 nc 3 pio2 b 19 nc 35 nc 51 dior_ o 4 pio0 b 20 hd_rst# o 36 test i 52 diow_ o 5 pio1 b 21 usb_pwr b 37 cs1_ o 53 dmarq i 6 dd11 b 22 reset# i 38 d_pwr_ctl b 54 dd15 b 7 dd4 b 23 dgnd p 39 5v_in p 55 dgnd p 8 dd10 b 24 agnd p 40 dvdd p 56 dvdd p 9 dvdd p 25 avdd3 p 41 cs0_ o 57 dd0 b 10 dgnd p 26 dm b 42 da2 o 58 dd14 b 11 dd5 b 27 dp b 43 u_rx b 59 dd1 b 12 dd9 b 28 agnd1 p 44 u_tx o 60 dd13 b 13 dd6 b 29 rref a 45 da0 o 61 dd2 b 14 dd8 b 30 avdd1 p 46 da1 o 62 gpio 1 b
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 12 15 dd7 b 31 x_power p 47 intrq i 63 f_led b 16 nc 32 xo b 48 dmack_ o 64 h_led b 3.3 pin descriptions table 3.3 ? 48 pin descriptions usb interface pin name pin# type description vref 21 a reference resistor dm 18 b hs d- dp 19 b hs d+ xo 24 b crystal output xi 25 i crystal input reset# 15 i (pu) external reset test 26 i (pd) test mode input ata/atapi interface pin name pin# type description dd0~15 43,45,47, 2,5,8,10,1 2,11,9,6,4, 1,46,44, 41 b (pd) ide data bus hd_rst# 13 o device reset cs1_, cs0_ 27,31 o chip select #1,#0 da0~2 33,34,32 o ide address #2,#1,#0 intrq 35 i (pd) ide interrupt input dmack_ 36 o ide acknowledge iordy 37 i (pu) ide ready dior_ 38 o ide read signal diow_ 39 o ide write signal dmarq 40 i (pd) ide request
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 13 miscellaneous interface pin name pin# type description gpio 1 48 b (pu) gpio pio0 3 b (pd) gpio power / ground pin name pin# type description 5v_in 29 p 5v input dvdd1,x-pow er,3v3_out, dvdd2 7,23,30,42 p digital vdd agnd1 16 p analog gnd agnd2 20 p analog gnd #1 avcc1 17 p analog vdd #3 avcc2 22 p analog vdd #1 miscellaneous pin name pin# type description usb_pwr 14 b (pu) usb power detect d_pwr_ctl 28 b (pd) hdd power control table 3.4 - 64 pin descriptions usb interface pin name pin# type description rref 29 a reference resistor dm 26 b hs d- dp 27 b hs d+ xo 32 b crystal output xi 33 i crystal input reset# 22 i (pu) external reset test 36 i (pd) test mode input
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 14 ata/atapi interface pin name pin# type description dd0~15 57,59,61, 2,7,11,13, 15,14,12, 8,6,1,60, 58,54 b (pd) ide data bus hd_rst# 20 o device reset cs1_, cs0_ 37,41 o chip select #1,#0 da0~2 45,46,42 o ide address #2,#1,#0 intrq 47 i (pd) ide interrupt input dmack_ 48 o ide acknowledge iordy 49 i (pu) ide ready dior_ 51 o ide read signal diow_ 52 o ide write signal dmarq 53 i (pd) ide request miscellaneous interface pin name pin# type description gopi 1 62 b (pu) general purpose io #1 pio 0 4 b (pd) program io #0 pio 1 5 b (pd) program io #1 becomes spidi when spi interface is e nabled (spidi : spi data input) pio 2 3 b (pd) program i/o #2 becomes spido when spi interface is enabled (spido : spi data output) u_rx 43 b (pu) uart rxd u_tx 44 o uart txd power / ground pin name pin# type description 5v_in 39 p 5v input dgnd 10,23,34,55 p digital gnd dvdd 9,31,40,56 p digital vdd agnd 24 p analog gnd agnd1 28 p analog gnd #1 avdd3 25 p analog vdd #3
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 15 avdd1 30 p analog vdd #1 miscellaneous pin name pin# type description usb_pwr 21 b (pu) usb power detect f_led 63 b (pu) operation mode indicator (full-speed) h_led 64 b (pu) operation mode indicator (high-speed) d_pwr_ctl 38 b (pd) hdd power control notation: type o output i input b bi-directional b/i bi-directional, default input b/o bi-directional, default output p power / ground a analog so automatic output low when suspend pu internal pull up pd internal pull down odpu open drain with internal pull up
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 16 chapter 4 block diagram ep0, ep3 fifo sie utm bulk fifo ide interface 8051 core spi device operation register usb spi interface 2k rom gpio ide device figure 4.1 - block diagram
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 17 chapter 5 function description 5.1 utm the usb 2.0 transceiver macrocell, it?s the analog circuitry that handles the low level usb protocol a nd signaling, and shifts the clock domain of the data from the usb 2.0 rate to one that is compatible wit h the general logic. 5.2 sie the serial interface engine, which contains the usb pid and address recognition logic, and other seque ncing and state machine logic to handle usb packets and t ransactions. 5.3 ep0/ep3 fifo endpoint 0/3 fifo: the control and interrupt fifo. it is composed of tx03fifo and rx03fifo, with 64-byte fifo each, and it is used for endpoint 0/3 data transfer. 5.4 bulk fifo it is constructed in interleaved architecture and c omposed by two data buffers which is used to store data transferred between usb host and ide device. 5.5 ide interface the ide engine is extended from standard ata / atap i protocol. it supports multiword dma mode, and ult ra dma mode data transfers. 5.6 operation register it is a register space to store status information and to control the functions of GL811S by 8051. 5.7 spi interface the serial peripheral interface is a serial, synchr onous communication protocol. it is compatible with motorola?s spi specifications.
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 18 chapter 6 electrical characteristics 6.1 absolute maximum ratings table 6.1 - maximum ratings symbol parameter min. max. unit v cc dc supply voltage +3.0 +3.6 v v i dc input voltage -0.3 v cc + 0.3 v v i/o dc input voltage range for i/o -0.3 v cc + 0.3 v v ai/o dc input voltage for usb d+/d- pins -0.3 v cc + 0.3 v v esd static discharge voltage 4000 v t a ambient temperature 0 100 o c 6.2 temperature conditions table 6.2 - temperature conditions item value storage temperature -50 o c ~ 150 o c operating temperature 0 o c ~ 70 o c 6.3 dc characteristics 6.3.1 i/o type digital pins table 6.3 - i/o type digital pins parameter min. typ. max. unit current sink @ v ol = 0.4v 10.58 14.21 16.87 ma current output @ v oh = 2.4v (ttl high) 14.74 27.46 43.0 ma falling slew rate at 30 pf loading capacitance 0.5 6 0.91 1.28 v/ns rising slew rate at 30 pf loading capacitance 0.5 8 0.91 1.72 v/ns schmitt trigger low to high threshold point 1.4 1.5 1.6 v schmitt trigger low to high threshold point 1.4 1.5 1.6 v pad internal pull up resister 37.87k 64.7k 108.11k ohms pad internal pull down resister 29.85k 59.45k 134.26k ohms
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 19 6.3.2 d+/ d- table 6.4 - d+/ d- parameter min. typ. max. unit d+/d- static output low (r l of 1.5k to v cc ) 0 0.3 v d+/d- static output high (r l of 15k to gnd ) 2.8 3.6 v differential input sensitivity 0.2 v single-ended receiver threshold 0.8 2.0 v transceiver capacitance 20 pf hi-z state data line leakage -10 +10 a driver output resistance 28 43 ohms 6.3.3 switching characteristics table 6.5 - switching characteristics parameter min. typ. max. unit x1 crystal frequency 11.97 12 12.03 mhz x1 cycle time 83.3 ns d+/d- rise time with 50pf loading 4 20 ns d+/d- fall time with 50pf loading 4 20 ns 6.4 ac characteristics- ata/ atapi the GL811S complies with ata / atapi-6 specification rev 1.0, which supports following data transfer modes : 1. dma (direct memory access) data transfer: dma data transfer means of data transfer between de vice and host memory without host processor intervention. - multiword dma: multiword dma is a data transfer pro tocol used with the read dma, write dma, read dma queued, write dma queued and packet c ommands. when a multiword dma transfer is enabled as indicated by i dentify device or identify packet device data, this data transfer protocol shall be u sed for the data transfers associated with these commends. (please refer to the ata / atapi-6 specif ication rev 1.0 for more information.) - ultra dma: ultra dma is a data transfer protocol us ed with the read dma, write dma, read dma queued, write dma queued and packet comman ds. when this protocol is enabled, the ultra dma protocol shall be used inste ad of the multiword dma protocol when these commands are issued by the host. this protocol appl ies to the ultra dma data burst only. (please refer to the ata / atapi-6 specification rev 1.0 fo r more information.) following listed the symbols and their respective d efinitions that are used in the timing diagram:
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 20 all signals are shown with the asserted condition f acing to the top of the page. the negated condition is shown towards the bottom of the page relative to the asse rted condition. the interface uses a mixture of negative and positi ve signals for control and data. the terms asserted and negated are used for consistency and are independen t of electrical characteristics. in all timing diagrams, the lower line indicates ne gated, and the upper line indicates asserted. the f ollowing illustrates the representation of a signal named te st going from negated to asserted and back to negat ed, based on the polarity of the signal. - signal transition (asserted or negated) - data transition (asserted or negated) - data valid - undefined but not necessarily released - asserted, negated or released - released - the ?other? condition if a signal is shown with no change
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 21 6.4.1 register transfers / pio data transfers notes: 1. device address consists of signals cs0_, cs1_ an d da(2:0). 2. data consists of iodd(7:0). 3. the negation of iordy by the device is used to e xtend the register transfer cycle. the determinatio n of whether the cycle is to be extended is made by the host after t a from the assertion of dior_ or diow_. the assertion and negation of iordy are described a s following: 3.1 device never negates iordy, devices keeps iordy rel eased: no wait is generated. 3.2 device negates iordy before t a , but causes iordy to be asserted before t a . iordy is released prior to negation and may be asserted for no more t han 5 ns before release: no wait generated. 3.3 device negates iordy before t a , iordy is released prior to negation and may be as serted for no more than 5 ns before release: wait generated. the cycle completes after iordy is released. for cycles where a wait is generated and dior_ is asser ted, the device shall read data on iodd(0:7) for t rd before asserting iordy. 4. dmack_ shall remain negated during a register trans fer.
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 22
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 23 6.4.2 multiword dma data transfer
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 24 note: the host shall not assert dmack_ or negate both cs0 _ and cs1_ until the assertion of dmarq is detected . the maximum time from the assertion of dmarq to the assertion of dmack_ or the negation of both cs0_ and cs1_ is not defined. figure 6.1 - initiating a multiword dma data burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 25 figure 6.2 - sustaining a multiword dma data burst note: to terminate the data burst, the device shall negat e dmarq within the t l of the assertion of the current dior_ or diow_ pulse. the last data word for the bu rst shall then be transferred by the negation of th e current dior_ or diow_ pulse. if all data for the c ommand has not been transferred, the device shall r eassert dmarq again at any later time to resume the dma ope ration. figure 6.3 - device terminating a multiword dma dat a burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 26 note: 1. to terminate the transmission of a data burst, the host shall negate dmack_ within the specified time after a dior_ or diow_ pulse. no further dior_ or d iow_ pulses shall be asserted for this burst. 2. if the device is able to continue the transfer of data, the device may leave dmarq asserted and wa it for the host to reassert dmack_ or may negate dmarq at any time after detecting that dmack_ has been negated. figure 6.4 - host terminating a multiword dma data burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 27 6.4.3 ultra dma data transfer table 6.5 - ultra dma data burst timing requirement s mode 0 (in ns) mode 1 (in ns) mode 2 (in ns) mode 3 (in ns) mode 4 (in ns) name min max min max min max min max min max comment t 2cyctyp 240 160 120 90 60 typical sustained average two cycle time t cyc 112 73 54 39 25 cycle time allowing for asymmetry and clock variations t 2cyc 230 154 115 86 57 two cycle time allowing for clock variations t ds 15 10 7 7 5 data setup time at recipient t dh 5 5 5 5 5 data hold time at recipient t dvs 70 48 30 20 6 data valid setup time at sender t dvh 6 6 6 6 6 data valid hold time at sender t fs 0 230 0 200 0 170 0 130 0 120 first storbe time t li 0 150 0 150 0 150 0 100 0 100 limited interlock time t mli 20 20 20 20 20 interlock time with minimum t ui 0 0 0 0 0 unlimited interlock time t az 10 10 10 10 10 maximum time allowed for output drivers to release t zah 20 20 20 20 20 minimum delay time required for output t zad 0 0 0 0 0 drivers to assert or negate t env 20 70 20 70 20 70 20 55 20 55 envelope time t sr 50 30 20 na na strobe to dmardy_ time t rfs 75 70 60 60 60 ready to final strobe time t rp 160 125 100 100 100 minimum time to assert stop or negate dmarq t iordyz 20 20 20 20 20 maximum time before releasing iordy t ziordy 0 0 0 0 0 minimum time before driving strobe t ack 20 20 20 20 20 setup and hold times for dmack_ t ss 50 50 50 50 50 time from strobe edge to negation of dmarq or assertion of stop
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 28 notes: the definitions for the diow_:stop, dior_:hdmardy_: hstrobe and iordy:ddmardy_:dstrobe signal lines are not in effi cient until dmarq and dmack are asserted. figure 6.5 - initiating an ultra dma data-in burst notes: iodd(15:0) and dstrobe signals are shown at both th e host and the device to emphasize that cable settl ing time as well as cable propagation delay shall not a llow the data signals to be considered stable at th e host until some time after they are driven by the device. figure 6.6 - sustained ultra dma data-in burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 29 notes: 1. the host may assert stop to request termination of the ultra dma burst no sooner than t rp after hdmardy_ is negated. 2. if the t sr timing is not satisfied, the host may receive zero , one, or two more data words from the device. figure 6.7 - host pausing an ultra dma data-in burs t notes: the definitions for the diow_:stop, dior_:hdmardy_: hstrobe and iordy:ddmardy_:dstrobe signal lines are no longer i n effect after dmarq and dmack are negated. figure 6.8 - device terminating an ultra dma data-i n burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 30 notes: the definitions for the diow_:stop, dior_:hdmardy_: hstrobe and iordy:ddmardy_:dstrobe signal lines are no longer i n effect after dmarq and dmack are negated. figure 6.9 - host terminating an ultra dma data-in burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 31 notes: the definitions for the diow_:stop, dior_:hdmardy_: hstrobe and iordy:ddmardy_:dstrobe signal lines are not in effe ct until dmarq and dmack are asserted. figure 6.10 - initiating an ultra dma data-out burs t notes: iodd(15:0) and hstrobe signals are shown at both th e device and the host to emphasize that cable settl ing time as well as cable propagation delay shall not a llow the data signals to be considered stable at th e devicet until some time after they are driven by the host. figure 6.11 - sustained ultra dma data-out burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 32 notes: 1. the device may negate dmarq to request terminati on of the ultra dma burst no sooner than t rp after ddmardy_ is negated. 2. if the t sr timing is not satisfied, the device may receive ze ro, one, or two more data words from the host. figure 6.12 - device pausing an ultra dma data-out burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 33 notes: the definitions for the diow_:stop, dior_:hdmardy_: hstrobe and iordy:ddmardy_:dstrobe signal lines are no longer i n effect after dmarq and dmack are negated. figure 6.13 - host terminating an ultra dma data-ou t burst
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 34 notes: the definitions for the diow_:stop, dior_:hdmardy_: hstrobe and iordy:ddmardy_:dstrobe signal lines are no longer i n effect after dmarq and dmack are negated. figure 6.14 - device terminating an ultra dma data- out burst 6.5 ac characteristics - usb 2.0 the GL811S conforms to all timing diagrams and spec ifications for universal serial bus specification r ev. 2.0. please refer to this specification for more informa tion.
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 35 chapter 7 package dimension control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d e d1 e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 9.00 basic 9.00 basic 7.00 basic 7.00 basic 0.354 basic 0.354 basic 0.276 basic 0.276 basic 0.05 1.35 1.40 1.60 0.15 1.45 0 0 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 0 0 11 11 3.5 12 12 7 13 13 0.063 0.006 0.057 0.055 0.002 0.053 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 5.50 basic 5.50 basic 0.020 basic 0.217 basic 0.217 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. 1 24 25 36 37 48 12 13 seating plane e b 4x 4x e e 1 e 2 a a b d c aaa b a d h bbb ddd m c b a s s d b d1 d2 d d a a2 a1 0 . 0 5 s l 1 c 0 1 - 0 - c c ccc gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h GL811S aaaaaaagaa ywwxxxxxxxx date code lot code internal no. version no. n : normal package g : green package figure 7.1 ? GL811S 48 pin lqfp package
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 36 16 control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d d1 e e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 12.00 basic 12.00 basic 10.00 basic 10.00 basic 0.472 basic 0.472 basic 0.393 basic 0.393 basic 0.05 1.35 1.40 1.60 0.15 1.45 00 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 00 11 11 3.5 12 12 7 13 13 0.063 0.006 0.057 0.055 0.002 0.053 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 7.50 basic 7.50 basic 0.020 basic 0.295 basic 0.295 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. seating plane e b 4x 4x 64 1 17 32 33 48 49 gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h e e 1 e 2 a a b d c aaa b a d h bbb ddd m c b a s s d b d1 d2 d d a a2 a1 0 . 0 5 s l 1 c 0 1 - 0 - c c ccc GL811S aaaaaaagaa ywwxxxxxxxx date code lot code internalno . version no. n : normal package g : green package figure 7.2 ? GL811S 64 pin lqfp package
GL811S usb2.0 to ata/atapi bridge controller ?2007 genesys logic inc. - all rights reserved. page 37 chapter 8 ordering information table 8.1 - ordering information part number package green version status GL811S-mngxx 48-pin lqfp green package xx available GL811S-msgxx 64-pin lqfp green package xx available

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